1. Field of the Invention
The invention relates to MNOS transistors and more particularly to arrays of dual gate MNOS memory transistors which present a substantially symmetrical load to a sensing circuit.
2. Description of the Prior Art
The threshold voltage of MNOS memory transistors can be shifted by selectively biasing the transistor. In utilizing these transistors as digital memories, the threshold voltage is selectively shifted between two levels which represent the two values of the digital signal to be stored. Shifting the threshold voltage causes the conductivity of the transistor to change for a given gate voltage. In most applications a plurality of MNOS memory transistors are arranged in arrays.
In typical prior art circuits, the MNOS memory transistor to be interrogated to determine its threshold state was enabled and utilized as the load of one transistor of a cross-coupled pair and a reference transistor was utilized as the load for the second transistor comprising the cross-coupled pair. Since the MNOS memory transistor interrogated was one member of an array, the loads of the transistors comprising the cross-coupled pair were grossly dissimilar, particularly with respect to the capacitive loading. This dissimilarity could be partially compensated for by selecting the geometry of the memory transistors with respect to the geometry of the reference transistor; however, the imbalance was always present and could lead to critical timing problems.